A lead frame for a semiconductor device comprises a stage for mounting a semiconductor chip, inner leads for electric connection to the electrodes of the semiconductor chip through wire bonding, and outer leads used as an external connection terminal when the semiconductor device is mounted on a substrate and the like. Here, it is desired that the stage has a good bonding property to the semiconductor chip, the inner leads have a good wire bonding property, and the outer leads have a good bonding property through soldering to a target member such as a substrate on which the semiconductor device is mounted.
FIG. 1 is a plan view illustrating one example of the lead frame for a semiconductor device. In the lead frame 10, reference numeral 12 denotes outer leads, 14 denotes inner leads, and 16 denotes a stage acting as a chip-mounting portion on which a semiconductor chip (not shown) is further mounted. The stage 16 is connected to rails 20 through support bars 18. Reference numeral 22 denotes a dambar.
As will be described later, after formation of the desired metal film on the lead frame 10, a semiconductor chip is mounted on the stage, and the semiconductor chip is connected to the inner leads through wire bonding. Finally, the semiconductor chip, wires and inner leads 14 are sealed with a resin to complete a semiconductor device. A solder film is previously formed on the outer leads 12 of the semiconductor device, or soldering is effected at the time of mounting the semiconductor device on the substrate.
Recently, in mounting the semiconductor devices on the substrates, the mounting process by using a solder free of lead (Pb) is generally carried out from the standpoint of protecting the environment. As the lead-free solder, there can be used, for example, a tin-zinc (Sn—Zn)-based solder, a tin-silver (Sn—Ag)-based solder and others.
As a lead frame for a semiconductor device, there has been known the so-called Pd-PPF (Pd-PrePlated frame) produced by plating palladium (Pd) or a Pd alloy film on a substrate consisting of Cu or a Cu alloy via a nickel (Ni)-plating layer as an underlayer and, further, forming a thin Au-plating film or a thin Ag-plating film thereon (see, JP-A-4-115558).
As another example of the lead frame for semiconductor devices having the above external plating layers, JP-A-4-337657 discloses a lead frame comprising an Ni-plating layer on the substrate of the lead frame, a Pd— or a Pd alloy-plating layer on at least the inner leads or the outer leads and, further, an Au-plating layer thereon. Further, JP-A-11-111909 discloses a plated lead frame having the similar plating layers as above, and JP-A-2001-110971 discloses a plated lead frame comprising an Ni-plated protection layer and a Pd— or a Pd alloy-plated intermediate layer formed on the substrate of the lead frame and, further, an outermost layer formed by alternately plating Pd and Au thereon. Furthermore, JP-A-2002-76229 discloses a plated lead frame produced by forming an Ni layer and a Pd layer on the substrate of the lead frame and then forming an Ag layer thereon, wherein the Ag layer can be completely melted into the Pd solder upon heating.